1. Field of the Invention
The present invention relates to a synchronous dynamic random access memory DRAM, and in particular to a delay locked loop DLL using a bidirectional delay.
2. Description of the Background Art
FIG. 1 illustrates a conventional synchronous mirror delay SMD used for a synchronous dynamic random access memory DRAM.
As shown therein, an one-shot pulse generator 10 receives an external clock signal CLKext, and generates an input clock signal CLKin having an one-shot pulse shape. A first delay unit 12 delays the input clock signal CLKin for a predetermined time d1+d2+dt. Here, the delay time d1+d2+dt by the first delay unit 12 is equal to a sum of the delay times by a mirror control circuit 16 and a second delay unit 22 to be described later.
A forward delay array 14 includes a plurality of unit delays consisting respectively of a NAND gate and an inverter. The forward delay array sequentially delays a clock signal FDAin outputted from the first delay unit 12, and outputs a plurality of delay clock signals FDA1.about.FDAn. One input of the NAND gate in each of the unit delays is fixed at the VCC level and the other input of the NAND gate is an output of the previous unit delay.
The mirror control circuit 16 consists of a plurality of NAND gates. The mirror control circuit 16 compares the input clock signal CLKin with the plurality of delay clock signals FDA1.about.FDAn outputted from the forward delay array 14, respectively, and generates pulse signals G1.about.Gn having an identical pulse width to the input clock signal CLKin at a point where the phases of the two clock signals are identical.
A backward delay array 18 has the same size and constitution as the forward delay array 14, delays the pulse signals G1.about.Gn generated from the mirror control circuit 16 in the backward direction for the time which the pulse signal has been generated, and outputs a clock signal BDAout having an identical phase to the input signal FDAin of the forward delay array 14.
A dummy load 20 is a load added so that the forward delay array 14 and the mirror control circuit 16 can be symmetric to the backward delay array 18 and a dummy load 20. The second delay unit 22 delays the clock signal BDAout outputted from the backward delay array 18 for a time d2, and outputs an internal clock signal CLKint having a phase identical to or faster than the input clock signal CLKin.
The operation of the conventional synchronous mirror delay SMD will now be described.
When the clock signal CLKext as shown in FIG. 2A is externally inputted, the one-shot pulse generator 10 generates the input clock signal CLKin as shown in FIG. 2B. The generated input clock signal CLKin is delayed in the first delay for a predetermined time d1+d2+dt, and becomes the input clock signal FDAin of the forward delay array 14, as shown in FIG. 2C.
The forward delay array 14 sequentially delays the clock signal FDAin through the unit delays thereof. The mirror delay circuit 16 sequentially compares the input clock signal CLKin outputted from the one-shot pulse generator 10 with the plurality of delay clock signals FDA1.about.FDAn outputted from the backward delay array 14, and generates the pulse signals G1.about.Gn at a point where the phases of the two clock signals are identical.
For example, it is presumed that the delay clock signal FDAi outputted from the i-th unit delay of the forward delay array 14, as shown in FIG. 2D, is synchronized with the input clock signal CLKin. Here, the i-th NAND gate of the mirror delay circuit 16 generates the pulse signal Gi having an identical pulse width to the input clock signal CLKin, as shown in FIG. 2E, and the outputs from the other NAND gates are at a high level. Accordingly, the pulse signal Gi proceeds in the backward direction from a synchronization point (the inverter of the i-th unit delay) through the backward delay array 18. However, since the pulse signal Gi is delayed more than the clock signal FDAin by the time tDA, a rising edge of the pulse signal Gi appears at a very lagging time, as compared with that of the external clock signal CLKext. As a result, the pulse signal Gi cannot be used as an internal clock signal CLKint for the system.
Accordingly, if the pulse signal Gi generated from the mirror delay circuit 16 is delayed for the time tDA through the backward delay array 18, the clock signal BDAout as shown in FIG. 2F is generated. Therefore, by setting a delay so that a delay of the second delay unit 22 is set smaller than a delay d2 of the unit delay, the internal clock signal CLKint having a faster phase than the external clock signal CLKext can be obtained from the clock signal BDAout.
Here, the delay of the second delay 22 is set to be d2 so that the delay time d1+d2+dt by the first delay unit 12 can be offset by the delay times of a last NAND gate of the mirror control circuit 16 and the second delay unit 22. Accordingly, as illustrated in FIG. 2G, the internal clock signal CLKint synchronized with the external clock signal CLKext is generated from the second delay unit 22, thereby being used as an internal signal for the system.
However, the conventional synchronous mirror delay SMD must be additionally provided with the backward delay array having an identical size to the forward delay array in order to generate a final clock signal synchronized with the external clock signal. As a result, the conventional synchronous mirror delay SMD has a disadvantage in that an area of the circuit is increased due to the added backward delay array.
In addition, in the conventional synchronous mirror delay SMD, increases power consumption by the added backward delay array. This phenomenon is serious in a standby mode where the synchronous mirror delay SMD must be at an operational state.